This invention relates in general to the field of electronics and more specifically to phase lock loops.
In emerging wireless communication systems such as third generation wideband code division multiple access (WCDMA), General Packet Radio Services (GPRS)/Global System of Mobile communications (GSM), etc. the requirements for small channel spacing and fast lock times makes designing a phase lock loop (PLL) design more and more difficult. In a conventional PLL, fast lock times and small channel spacing is usually achieved by using a fractional N PLL, which enables a higher reference compare frequency, and wider loop filter bandwidth. A fractional N PLL implementation however has some limitations as it introduces fractional spurs that will put a limit on how wide the loop filter can be, and therefore will also limit the overall lock time.
In these new wireless applications, a PLL may also need high gain to compensate for temperature drift which will degrade and impact the phase noise and spurious levels of the overall design. Given the above problems, there exists a need in the art for a low spurious PLL that can achieve very fast lock times. It would also be beneficial to provide a PLL that requires no charge pumps and generates no fractional spurs.